Teruo Higashino's Recent Research No.6 (Osaka Univ., Japan)

Teruo Higashino

Professor, Osaka University, Japan

Osaka University
Graduate School of Information Science and Technology
Yamadaoka 1-5, Suita, Osaka 565-0871

(6) High-reliable Real-time System Design

    real-time-systems2.png RTSS.jpg

Recently, due to the growth of the complexity of computer systems and the requirements to the shorter time-to-market, it is required to develop a methodology to effectively design a complex system in a shorter time that performs efficiently and still meets the required specification. Especially, for real-time systems, it is required to meet several specified real-time constraints. To cope with such a problem, we are developing a technique using parametric model checking, to derive automatically a condition formula for design parameters (such as execution delay, timeout value, etc.). Moreover, we are studying on analysis, performance evaluation, and cost- and power-optimized automatic synthesis of communication structure of System-on-Chip (SoC) and/or Network-on-Chip (NoC), considering communication scheduling, topology, and protocols to meet given real-time constraints.

[Selected Publications]
Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata and Teruo Higashino : "A Real Time Budgeting Method for Module-Level-Pipelined Bus Based System using Bus Scenarios", Proc. of 43rd ACM/IEEE Design Automation Conference (DAC 2006), pp.37-42, 2006.

Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino : "A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata", International Journal of Foundations of Computer Science, Vol.17, No.4, pp.833-850, 2006.

Tomoya Kitani, Yoshifumi Takamoto, Keiichi Yasumoto, Akio Nakata and Teruo Higashino : "A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems", Proc. of 25th IEEE Int. Real-Time Systems Symposium (RTSS 2004), pp.437-446, 2004.

Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata and Teruo Higashino: "Design and Implementation of Priority Queuing Mechanism on FPGA using Concurrent Periodic EFSMs and Parametric Model Checking", Proc. of13th Int. Conf. on Field Programmable Logic and Applications (FPL 2003), pp.1145-1148, 2003.

Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori,Keiichi Yasumoto, Akio Nakata and Teruo Higashino: "Design and Implementation of FPGA Circuits for High Speed Network Monitors", Proc. of 12th Int. Conf. on Field Programmable Logic and Applications (FPL 2002), pp. 393-403, 2002.

Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima, Teruo Higashino and Kenichi Taniguchi: "Hardware Implementation of Communication Protocols modeled by Concurrent EFSMs with Multi-way Synchronization", Proc. of 37th ACM/IEEE Design Automation Conference (DAC-2000), pp. 762-767, 2000.